Maintaining low power consumption in portable electronic devices such as mobile phones, MP3 players and digital cameras becomes more challenging as these devices achieve higher levels of functionality. An increase in processing power and speed for these devices often requires a corresponding increase in the number of circuit devices, an increase in clock frequencies at which these circuit devices operate, and an increase in overall power consumed by these circuits.
A few techniques have been used to manage power consumption of integrated circuits (ICs). Multiple supply voltages (MSV) are used to power different sections of the IC based on their power requirements. For example, a section of the IC that performs computation can be powered at a lower supply voltage than a section of the IC devoted to an input-output (I/O) interface. Dynamic voltage scaling (DVS) is used to vary the supply voltage of sections of the IC based on a mode of operation, can also be used. For example, a memory component may be operated at a higher supply voltage during a write operation then during a read operation. Furthermore, clock gating (CG) is used to disable unused sections of an integrated circuit by disabling a local clock signal. For example, sections of a digital camera chipset responsible for data compression can be disabled during times when picture compression is not being performed by disabling a clock signal to the data compression circuits. By eliminating logic transitions, dynamic power consumption due to the charging and discharging of internal node capacitance is reduced.
Because of shrinking device geometries, and their corresponding increase in circuit density, static leakage current has become a more dominant factor in power consumption. Consequently, a circuit or logic block that has been shut down only by clock gating has the potential to still consume an appreciable amount of power due to static leakage current. One solution to the problem of static leakage current is to disable the power supply of the unused block. One difficulty with shutting down a power supply to a circuit is maintaining an interface logic on the boundary between a section of the IC that has a disabled power supply and another section of the IC that has an enabled power supply. Logic that bridges such a boundary can be subject to difficulties which include indeterminate states due to floating nodes, leakage current in interface devices between the two power domains, and lack of retention of logic states within disabled blocks.
What is needed are power efficient systems and methods of interfacing between power domains.